Enabling VIV DRC Checks

Zynq 7000 SoCs or 7 Series FPGAs Isolation Design Flow Lab (Vivado Design Suite) (XAPP1256)

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1.3 English
Note: Vivado Isolation Verifier (VIV) 2.0 is used to run design rule checks (DRCs) for IDF flow. See the Vivado Isolation Verifier User Guide (UG1291) for details on the DRCs. Enable VIV DRCs by running the following command from the TCL Console: set_param hd.enableIDFDRC true.
Important: For Vivado versions 2021.1 and later releases, skip ahead to Step 2. The VIV DRCs are automatically enabled by the tool when it detectsHD.ISOLATED set to true.
  1. Open the implementation run from the Flow Navigator menu tree, if not already open. To open, expand Implementation from the tree and select Open Implemented Design. The Flow Navigator is located on the left side of the Vivado GUI.
    Important: If the option Open Implemented Design is not available, it is either already open or there is no Implementation run available (requiring implementation to be re-run).
  2. Under the Implemented Design expand the Implementation section from the menu tree, select Report DRC as shown in the following figure.
    Figure 1. Running DRCs after Implementation
  3. Complete the following steps, as shown in the following figure:
    1. Uncheck all DRC rules (deselect All Rules).
    2. Expand all of the Isolation rules.
    3. Select IDF rules 1–6 (IDF Floorplan rules).
    4. Change the Results name field to viv_floorplan.
    5. Change the Output File field to c:/xilinx_design/viv_floorplan.txt.
    6. Select OK.
      Figure 2. VIV IDF Floorplan Rules (DRCs)
  4. All results are stored in the specified file (c:/xilinx_design/viv_floorplan.txt). For easier access, however, they are displayed in the DRC tab at the bottom of the Vivado GUI as shown in the following figure.
    Note: The DRC tab is only available after a DRC run has been executed.
    Figure 3. DRC Tab after VIV Floorplan Run
  5. Inspect the results (44 violations are identified).
    1. IDF-1 (Provenance): IDF-1 documents the circumstances under which a DRC report was generated, including tool versions, date, design name, user, platform, and host. This DRC is informational. No errors are reported here.
    2. IDF-2 (I/O bank violation): IDF-2 reports all I/O banks that have IOBs from more than one isolated region. Two I/O banks are used in this lab design and both contain IOBs from two distinct isolated regions, hence the two IDF-2 errors shown in the DRC run. I/O bank sharing is not an actual error. It is informational. There are some cases where I/O banks cannot be shared and some where they can. It depends on the user application and if that application allows a common I/O power supply between isolated regions.
    3. IDF-3 (Package pin violation): IDF-3 reports errors where pins from different isolated regions are adjacent to each other at the package level. This lab has 31 pin adjacency errors. These are real errors and would be unacceptable for any design desiring physical isolation between such regions.
    4. IDF-4 (Floorplan violation): IDF-4 reports all locations where one (or more) isolated region is either adjacent or overlaps another isolated region. There are no such violations in this design.
    5. IDF-5 (Placement violation): IDF-5 reports all placement violations. IDF-5 checks that no isolated logic or interconnect tile is adjacent to an isolated logic or interconnect tile of a different isolation group. There are no such violations in this design.
    6. IDF-6 (Routing violation): IDF-6 reports all routing violations and consists of three checks:
      1. All inter-region nets must have loads in exactly one isolated region.
      2. No inter-region net can use nodes that have programmable interconnect points (PIPs) in the fence, except clock nets which can have unused PIPs in the fence.
      3. For any tile containing inter-region nets, all such nets must have a common source and load.

    There are no such violations in this design.

    Note: Isolation groups are defined by Pblocks marked with the HD.ISOLATED property.
    Note: The DRC engine reports 44 violations, but only 36 can be accounted for. This discrepancy is due to the way the DRC engine counts violations. Any report (such as saying no violations found) increments the DRC rule violation counter. As such, the first missing violation is from IDF-1 where VIV outputs the provenance of the design, while the second, third, and fourth missing violations are from IDF-4, IDF-5, and IDF-6 reporting that no violations were found.
  6. Select each violation as desired, and notice that the violation is highlighted in the Vivado GUI.