Design Elaboration

Zynq 7000 SoCs or 7 Series FPGAs Isolation Design Flow Lab (Vivado Design Suite) (XAPP1256)

Document ID
XAPP1256
Release Date
2023-12-21
Revision
1.3 English

Register-transfer level (RTL) design elaboration is a small step in this lab. Its primary function is to debug the HDL code of the design as shown in the following figure.

Figure 1. Lab Flow Progression - RTL Elaboration