Creating an IP Integrator Block Design

Zynq 7000 SoCs or 7 Series FPGAs Isolation Design Flow Lab (Vivado Design Suite) (XAPP1256)

Document ID
XAPP1256
Release Date
2023-12-21
Revision
1.3 English

The purpose of using IP integrator in this lab is to demonstrate the ease with which a hierarchy can be added to a flat design (one not originally intended to be implemented using IDF). Additionally, it turns creating a redundant design into a copy/paste operation.

  1. Right-click the Diagram canvas and select Add IP.
  2. Scroll to the ZYNQ7 Processing System IP, select it, and press Enter (see the following two figures).
    Figure 1. Add IP > ZYNQ7 Processing System
  3. Repeat Step 1 for the keccakCompare_v1_0 IP (see the following figure).
  4. Repeat Step 1 for the keccak_v1_0 IP (see the following figure).
    Figure 2. IP Integrator Canvas after IP Selection

    Now that all the necessary blocks have been added (see the previous figure), it is time to start constructing the design. First, the processor is configured. In this lab, the processor’s sole function is to source the clocks and resets to your design.

  5. Save the design.
  6. Double-click the processing_system7_0 IP instance (to re-customize the IP).
    1. Under PS-PL Configuration, expand the AXI Non Secure Enablement > GP Master AXI Interface item and deselect the M AXI GP0 interface.
    2. In the Search box at the top, enter reset and select FCLK_RESET0_N (default) and FCLK_RESET1_N.
    3. Under Clock Configuration, expand the PL Fabric Clocks item and select FCLK_CLK0 (default), FCLK_CLK1, and FCLK_CLK2. Keep their default parameters for these clocks.
    4. Select OK.
    5. With the processor block still selected, select Run Block Automation at the top of the IP integrator canvas (navigating the mouse to select processing_system7_0/).
    6. Click OK to run block automation. The canvas should look like the following figure.
    Figure 3. IP Integrator Canvas after Running Block Automation
  7. Wire up the first instance of the Keccak hash block.
    1. Point at dout[15:0] of the keccak_0 instance until the mouse arrow turns into a pencil. Click and drag the wire to the data0[15:0] port of the keccakCompare_0 instance.
    2. Repeat Step a connecting dout_valid to data0_valid.
    3. Right-click buffer_full and select make external.
    4. Repeat Step c for ready.
    5. Repeat Step c for start.
    6. Repeat Step c for din[15:0].
    7. Repeat Step c for din_valid.
    8. Repeat Step c for last_block.
  8. Wire up the second instance of the Keccak hash block. In this case, you must first create it.
    1. Right-click keccak_0 and select Copy. Select elsewhere on the canvas, right-click, and select Paste.
    2. Point at dout[15:0] from the keccak_1 instance until the mouse arrow turns into a pencil. Click and drag the wire to the data1[15:0] port of the keccakCompare_0 instance.
    3. Repeat Step b connecting dout_valid to data1_valid.
    4. Right-click buffer_full and select make external.
    5. Repeat Step d for ready.
    6. Repeat Step d for start.
    7. Repeat Step d for din[15:0].
    8. Repeat Step d for din_valid.
    9. Repeat Step d for last_block.
  9. Wire up the compare block.
    1. Right-click match_PAD and select make external.
    2. Repeat Step a with matchB_PAD.
    3. Repeat Step a with errorInject_PAD.
  10. Save the design.
  11. Right-click an empty space in the canvas and select Regenerate Layout. The IP integrator canvas should look like the following figure:
    Figure 4. IP Integrator Canvas after Initial Connections
  12. Connect the clocks and resets.
    1. Draw a wire from FCLK_CLK0 of the processing_system7_0 IP to the clk input of the keccak_0 instance.
    2. Draw a wire from FCLK_RESET0_N of the processing_system7_0 IP to the rst_n input of the keccak_0 instance.
    3. Repeat Step a and Step b for the keccak_1 instance using FCLK_CLK1 and FCLK_RESET1_N, respectively.
    4. Draw a wire from FCLK_CLK2 of the processing_system7_0 IP to the clk input of the keccakCompare_0 instance.
    5. Click Save.
    6. Select Regenerate Layout. This is for ease of viewing. Your canvas should now look like the following figure.
      Figure 5. IP Integrator Canvas after Final Connections
  13. Each of the four blocks in the previous figure are modules that need to be isolated.
    Important: IP integrator introduces some design complexities by automatically adding DONT_TOUCH properties on every design block of an IP integrator design. This conflicts with IDF where multi-regional nets are concerned. To split multi-regional nets to meet IDF rules, the tools must modify the design by adding LUT buffers. However, DON’T_TOUCH prevents any modification by the tools. Much of this complexity can be minimized by adding a wrapper around modules intended for isolation. Ultimately, it is the wrapper that is marked as isolated. Such wrappers are not required for custom HDL designs not implemented using IP integrator.
  14. Right-click keccakCompare_0 and select Create Hierarchy …
    1. Name it keccakCompare_0_ISO_Wrapper.
    2. Make sure the check box to add the selected instance is selected and select OK.
  15. Repeat Step 14 for keccak_0 naming it keccak_0_ISO_Wrapper.
  16. Repeat Step 14 for keccak_1 naming it keccak_1_ISO_Wrapper.
  17. Repeat Step 14 for processing_system7_0 naming it ps7_ISO_Wrapper.
    Note: A critical message pops up noting that it is necessary to associate ELF files. Select OK. There are no such files in this project and they would get regenerated anyway in future steps.
  18. Verify all connections are valid by right-clicking on the blank canvas and selecting Validate Design. Select OK to continue.
  19. Save the design.
  20. Select Regenerate Layout. This is for ease of viewing. Your canvas should now look like the following figure.
    Figure 6. Final IP Integrator Canvas
  21. Generate all necessary output products for the block design you just created.
    1. In the Sources tab, right-click design_1 and select Create HDL Wrapper as shown in the following figure. On the pop-up window, select Let Vivado manage the wrapper and auto-update and select OK.
    2. Under the IP Integrator menu on the left, select Generate Block Design as shown in the following figure. Select Generate on the pop-up window. Select OK when the process completes.
      Note: Recall the critical warning with respect to ELF files. This warning is addressed in this step.
  22. The design is now ready for the RTL elaboration phase. Save the design.
    Figure 7. Create HDL Wrapper/Generate Block Design