Creating a Vivado IP Integrator Project

Zynq 7000 SoCs or 7 Series FPGAs Isolation Design Flow Lab (Vivado Design Suite) (XAPP1256)

Document ID
XAPP1256
Release Date
2023-12-21
Revision
1.3 English

This section describes the steps that take you through a bottom-up synthesis flow, using the Vivado Design Suite, which is the flow used for IDF designs to maintain isolation. Vivado allows you either to create designs manually or import register-transfer level (RTL) source code directly into the project so the project can be done using the Vivado tool. Refer to the Lab Flow Progression flow chart in the following figure.

Figure 1. Lab Flow Progression – Vivado IP Integrator Project