Constraint Checking (VIV - Constraints)

Zynq 7000 SoCs or 7 Series FPGAs Isolation Design Flow Lab (Vivado Design Suite) (XAPP1256)

Document ID
XAPP1256
Release Date
2023-12-21
Revision
1.3 English

On the floorplan, VIV checks the following:

  • Pins from different isolation groups are not physically adjacent, vertically or horizontally, at the die.
  • Pins from different isolation groups are not physically adjacent at the package. Adjacency is defined in eight compass directions: north, south, east, west, northeast, southeast, northwest, and southwest.
  • Pins from different isolation regions are not co-located in an I/O block (IOB) bank.
    Note: Though VIV does fault such conditions, only specific security-related applications require such bank isolation. The majority of applications allow for sharing of banks. Bank sharing is dependent on the specific application.
  • The Pblock constraints in the XDC file are defined so that a minimum of a one tile wide fence exists between isolated regions.