The UHD-SDI wrapper has three parameters:
- FXDCLK_FREQ
- This integer parameter specifies the frequency of the clock connected to the wrapper's clk_in port in Hz. The default value is 27000000 (27 MHz). The clk_in clock is used for timing purposes in the UHD-SDI wrapper and also as a reference frequency to compare against the GTX RX recovered clock to determine the RX bit rate. If the FXDCLK_FREQ parameter does not match the frequency of the clock on clk_in, then these functions are compromised.
- DRPCLK_PERIOD
- This integer parameter specifies the period of the clock connected to the wrapper's drpclk_in port in ns. The actual period of the clock must be rounded down to the next lowest integer. The drpclk_in clock is used for to generate some timing delays, such as the timeout periods of the GTX resets.
- INCLUDE_RX_EDH_PROCESSOR
- This parameter must be specified as a string, either "TRUE" or "FALSE". If this parameter is "TRUE", the EDH processor is included in the UHD-SDI RX core. If the parameter is "FALSE", the EDH processor in the RX section of the UHD-SDI core is omitted.