Download the reference design files for this application note from the AMD website.
Tool Flow and Verification
The following checklist indicates the tool flow and verification procedures used for the provided reference design.
| Parameter | Description |
|---|---|
| General | |
| Target devices | 7 series FPGA with GTX transceivers |
| Source code provided? | Yes |
| Source code format (if provided) | Verilog |
| Design uses code or IP from existing reference design, application note, third party or Vivado software? If yes, list. | Yes, IP cores from Vivado IP catalog |
| Simulation | |
| Functional simulation performed | No |
| Timing simulation performed? | No |
| Test bench provided for functional and timing simulation? | No |
| Test bench format | N/A |
| Simulator software and version | N/A |
| SPICE/IBIS simulations | N/A |
| Implementation | |
| Synthesis software tools/versions used | Vivado Design Suite 2018.1 |
| Implementation software tool(s) and version | Vivado Design Suite 2018.1 |
| Static timing analysis performed? | Yes |
| Hardware Verification | |
| Hardware verified? | Yes |
| Platform used for verification | KC705 |