The 270 Mb/s bit rate of SD-SDI is below the minimum line rate supported by the GTX RX. To receive 270 Mb/s SD-SDI, the GTX RX is used as an asynchronous oversampler to sample the SD-SDI bit stream at 11 times 270 Mb/s (2.97 gigasamples per second (GSPS)) without regard to where bit transitions occur. The CDR unit in the GTX RX is locked to the reference clock by asserting the GTX rxcdrhold input port High. This prevents the CDR from trying to lock to the slow SD-SDI signal and results in more uniform oversampling of the SD-SDI signal.
A data recovery unit (DRU), implemented in the programmable logic of the FPGA, examines the oversampled SD-SDI data from the GTX RX, determines the best sample to use for each bit, and outputs the recovered data. This DRU is not part of the SDI core, but is provided as part of this applications note's control module.
The DRU provided with this application note is described in Clock and Data Recovery Unit based on Deserialized Oversampled Data (XAPP1240). That application note does describe the theory of operation of the DRU, but is not necessary for use of the DRU in the UHD-SDI reference design.
SMPTE ST 259 (the SD-SDI standard) specifies several other bit rates besides 270 Mb/s. The DRU is instantiated into the SDI control module so as to support only 11X oversampling of 270 Mb/s serial data. However, if other SD-SDI bit rates must be supported by the application, the DRU can used to receive those bit rates, as well. Because that DRU supports fractional oversampling factors, it is possible to receive the other SD-SDI bit rates without requiring any additional RX reference clock frequencies. Note that the 540 Mb/s SD-SDI bit rate specified by SMPTE ST 344 is within the supported line rate range of the GTX transceiver and thus the GTX RX does not need to use the DRU to receive it. However, receiving the 540 Mb/s bit rate without the DRU requires a different reference clock frequency than is used for the other SDI bit rates. Thus, it is usually more convenient to use the DRU to receive the 540 Mb/s ST 344 signal using 5.5X oversampling so that the standard SDI reference clock frequency can be used. AMD does not have an example design supporting additional SD-SDI bit rates.
The DRU does not recover a clock and, because the CDR unit in the GTX RX is locked to its reference clock, the RXOUTCLK is not locked to the incoming bit rate in SD-SDI mode. The DRU does produce a data strobe indicating when a 10-bit data word is ready on its output. This data strobe is used by the SDI core to generate a clock enable that is asserted at a 27 MHz rate, typically with a 5/6/5/6 cadence relative to the rxoutclk clock from the GTX. The rx_ce_out output of the SDI wrapper is derived from the DRU data strobe and has the same cadence. Occasionally the cadence of the DRU data strobe and the rx_ce_out signal varies from the typical 5/6/5/6 cadence. This occurs when the DRU must make up for the slight difference between the actual SD-SDI bit rate and the frequency of the local reference clock provided to the GTX RX.
The following figure is a screen capture from an oscilloscope showing the 27 MHz rx_ce_out signal. The scope is triggered on the rising edge of rx_ce_out at the center of the screen. The scope is in infinite persistence mode and the waveform was allowed to accumulate for several minutes. The waveform is temperature-coded from red, indicating the most common position of the signal, to blue, indicating the least common position. The incoming SD-SDI signal that was used to create this screen capture was asynchronous to the local reference clock used by the GTX receiver. The rx_ce_out pulses on either side of the center pulse are always 5 or 6 clock cycles away from the center pulse because of the 5/6/5/6 cadence of the rx_ce_sd signal.
The two pulses at the far right and far left of the trace are nominally 11 clock cycles from the center pulse because of the 5/6/5/6 cadence. The nominal position is marked by the yellow and red pulse. And for the far right pulse, the dashed yellow vertical cursor marks the position that is 11 clock cycles from the rising edge of the center pulse. The nominal locations of the central yellow/red pulses are surrounded on either side by blue pulses indicating that, occasionally, the DRU must make the period of the rx_ce_sd cycle either 10 clock cycles or 12 clock cycles long to compensate for the frequency differences between the local reference clock and the incoming SD-SDI signal.
The SD-SDI DRU is supplied with this application note as an encrypted VHDL file. The encryption used on the DRU is compatible with most synthesis and simulation software.