12G-SDI support on 7 series GTX transceivers imposes additional requirements on clocking and limitations on operation of the transceivers. These requirements and limitations are:
- Only the QPLL can be used as the clock source for any RX and TX operating at 12G-SDI and the QPLL must be operating in range 2.
- The 7 series GTX RX has not been characterized at 3G-SDI and HD-SDI rates with the QPLL operating in range 2. When the QPLL is operating in range 2, any GTX RX must use the CPLL as its clock source for 3G-SDI and HD-SDI. TX units might use the QPLL to transmit 3G, HD, or SD even if it is operating in range 2.
- At 12G-SDI line rates, the GTX CDR only has ±200 ppm tolerance. Thus, the QPLL must have a 148.5 MHz reference clock when the transceivers in the Quad are running at the 11.88 Gb/s line rate and it must have a 148.5/1.001 MHz reference clock when the transceivers in the Quad are running at 11.88/1.001 Gb/s line rate.
- Because there is only a single QPLL available in the Quad, it is not possible to support both 11.88 Gb/s and 11.88/1.001 Gb/s 12G-SDI line rates simultaneously in the same Quad.
There are several strategies for working with the 12G-SDI clocking restrictions. If these restrictions are too cumbersome for a particular application, consider using the AMD Kintex™ UltraScale™ device. The Kintex UltraScale device has two QPLLs per GTH Quad, making it possible to support mixed operation at both 12G-SDI rates simultaneously in the same Quad.
Some applications might only need to support one 12G-SDI line rate at a time and not dynamically change between the two 12G-SDI rates. In other words, in 12G-SDI mode, all transceivers in the Quad only operate at either 11.88 Gb/s or 11.88/1.001 Gb/s and never switch back and forth between these two line rates. In this use case, all other SDI line rates can be supported, including any mix of integer and fractional frame rates at 6G-SDI and slower.
In this use case, shown in the following figure, the QPLL is given a single reference clock frequency, which can be either 148.5 MHz or 148.5/1.001 MHz, depending on which 12G-SDI line rate is to be supported (148.5 MHz for 11.88 Gb/s or 148.5/1.001 MHz for 11.88/1.001 Gb/s). In the example shown in the figure, the Quad only supports 11.88 Gb/s, so the QPLL reference clock frequency is 148.5 MHz. The QPLL operates in range 2 at 11.88 GHz and provides a 5.94 GHz clock to each transceiver in the Quad. (The transceivers always use a clock from the PLLs that is exactly one half the line rate).
The CPLLs are all given the other reference clock frequency, the one not given to the QPLL. In this example, the CPLLs are given the 148.5/1.001 MHz reference clock and operate at 2.97/1.001 GHz, providing a clock to each transceiver.
Any RX or TX in the Quad running at 11.88 Gb/s must use the QPLL clock as its serial clock source and have its PLL divider set to divide by 1. At 6G-SDI rates, the RX can use either the QPLL or the CPLL as long as the correct divider value is used (divide by 1 when using the CPLL and divide by 2 when using the QPLL). At 3G-SDI rates and lower, the RX must use the CPLL because the QPLL is in range 2. The TX units use the QPLL when transmitting integer frame rate SDI line rates and the CPLL when transmitting non-integer frame rate SDI lines rates. In this scenario, the only limitation is that only the 11.88 Gb/s 12G-SDI line rate is supported. It is not possible to transmit or receive at 11.88/1.001 Gb/s given the arrangement of the reference clocks.
If the QPLL is given the 148.5/1.001 MHz reference clock and the CPLL is given the 148.5 MHz reference clock, this use case supports the 11.88/1.001 Gb/s line rate, but not the 11.88 Gb/s line rate. All slower line rates can be supported.
If dynamic switching between the two 12G-SDI line rates is a requirement, things get much more complicated. Dynamic switching is possible, but has significant implications.
To support dynamic switching between the two 12G-SDI line rates, the reference clock to the QPLL must be dynamically switched between 148.5 MHz and 148.5/1.001 MHz. Anytime the reference clock frequency to the QPLL is dynamically switched, the QPLL must be reset. The single 12G-SDI line rate supported by the entire Quad at any point in time is dictated by which reference clock frequency is given to the QPLL. Thus, it is possible to switch the entire Quad between 11.88 Gb/s and 11.88/1.001 Gb/s, but all transceivers in the Quad running in 12G-SDI mode always run at the 12G-SDI line rate dictated by the frequency of the QPLL reference clock. It is not possible to have some units in the Quad running at 11.88 Gb/s and others at 11.88/1.001 Gb/s. Of course, it is possible to have different GTX Quads running at different 12G-SDI line rates, but all transceivers in one Quad must all run at the same line rate when running in 12G-SDI mode.
Any RX unit that is using the QPLL as the serial clock source for 6G-SDI becomes upset when the reference clock to the QPLL is dynamically switched between reference clock frequencies and reset. Any TX unit in the Quad that is using the QPLL as the serial clock source not only experiences an upset when the QPLL is reset, but also experiences a 1000 ppm shift in line rate as a result of the QPLL changing reference clock frequencies.
Thus, for most applications, support for dynamic switching between the two 12G-SDI line rates is problematic. The application can never support operation at both 12G-SDI line rates in the same GTX Quad simultaneously. And, any switch between 12G-SDI line rates impacts all transceivers in the Quad using the QPLL at the time of the switch.
There are several possible use cases where dynamic switching between 12G-SDI line rates may be practical. One such use case is shown in the following figure. In this use case, each transceiver is used in one direction only, either as a receiver or as a transmitter. The top two transceivers in the figure are RX-only and the bottom two transceivers are TX-only. When operating at 6G-SDI line rates and slower, each RX or TX always uses its CPLL. The CPLL is dynamically switched between the two reference clocks as required using the CPLLREFCLKSEL port. Any RX or TX unit running at 12G-SDI rates, must use the QPLL as the clock source. The QPLL can be dynamically switched between the two reference clock frequencies as required. But all units operating in 12G-SDI mode at that time switch between the two 12G-SDI line rates simultaneously as the QPLL dynamically switches between reference clock frequencies. Any mix of RX and TX units in the Quad could be supported this way; it doesn't have to be two RX and two TX.
The reason for limiting each transceiver to just RX or just TX and not both is to make it easier to use the CPLL. Because the CPLL is needed for both RX and TX, sharing the CPLL is somewhat difficult. Anytime the CPLL is dynamically switched between reference clock sources to change the TX line rate, it would temporarily disrupt the RX if they were both active and using the clock from the CPLL. If, however, the application doesn't care that both the RX and TX are affected by dynamically switching the CPLL between the two reference clock frequencies, then it would be possible to use a transceiver to transmit and receive at the same time.