The GT wizard generates a GTX common wrapper when the GTX wrapper example design is generated. That GT wizard configures the QPLL in the GTX common module according to the parameters entered into the GTX wizard. If the maximum line rate supported is 6G-SDI, the QPLL is configured for operation in range 1. If the maximum line rate supported is 12G-SDI, the QPLL is configured for operation in range 2. This is important to understand because the UHD-SDI wrapper must be told which range the QPLL is configured for to properly control the GTX.
The UHD-SDI wrapper has several ports for both the RX and the TX which are related to the configuration and selection of the PLLs. For the TX section, these ports are:
- tx_pll_select_in
- This port selects which PLL is to be used as the serial clock source for the GTX TX. This port can be changed dynamically to change the TX clock source. Whenever, tx_pll_select_in changes, the UHD-SDI wrapper changes the TXSYSCLKSEL port of the GTX to change the selected PLL. And, the UHD-SDI wrapper also resets the GTX TX. The PLL selected by the value on tx_pll_select_in is not fixed, but is controlled by the tx_pll_type_in port.
- tx_pll_type_in
- Bit 0 of this port specifies which PLL is used when tx_pll_select_in is Low. Bit 1 of this port specifies which PLL is used when tx_pll_select_in is High. The CPLL is selected if the tx_pll_type_in bit is Low and the QPLL is selected if the tx_pll_type_in bit is High. So, for example, consider the case where the application uses the CPLL when tx_pll_select_in is Low and the QPLL when tx_pll_select_in is High. The application hardwires a value of 2'b10 on the tx_pll_type_in port specifying use of the CPLL when tx_pll_select_in is Low and the QPLL when tx_pll_select_in is High. The tx_pll_type_in port is usually statically configured by hardwiring the bits of the port. However, the SDI control logic does support and respond to dynamic changes on the tx_pll_type_in port.
- tx_pll_range_in
- Bit 0 of this port specifies the operating range of the TX PLL (0 = range 1, 1 = range 2) when tx_pll_select_in is Low. Bit 1 of this port specifies the operating range of the TX PLL when tx_pll_select_in is High. The CPLL is always considered to be in range 1. As an example, consider the case where the QPLL is used in range 2 and is selected when tx_pll_select_in is High and the CPLL is selected when tx_pll_select_in is Low. A value of 2'b10 must be applied to the tx_pll_range_in port of the UHD-SDI wrapper. Bit 0 is Low because the CPLL is selected when tx_pll_select_in is Low and the CPLL is always considered to be in range 1. Bit 1 is High because the QPLL is selected when tx_pll_select_in is High and, in this example, the QPLL is configured for range 2.
The UHD-SDI wrapper has exactly the same set of ports as just described for the RX section. These ports are named rx_pll_select_in, rx_pll_type_in, and rx_pll_range_in. They behave the same way as the TX ports, but operate on the RX section instead of the TX section by controlling the RXSYSCLKSEL port of the GTX and the RX PLL divider.
The UHD-SDI wrapper has two PLL reset outputs called rx_pll_reset_out and tx_pll_reset_out. These are generated by the SDI control logic to reset the QPLL and the CPLL. These reset outputs are asserted automatically during the power-on initialization sequence of the GTX executed by the SDI control logic and also during full GTX TX and RX reset sequences initiated by the assertion of the tx_gtx_full_reset_in and rx_gtx_full_reset_in ports of the UHD-SDI wrapper. It is up to the application to properly connect the rx_pll_reset_out and the tx_pll_rest_out ports to the proper PLL reset inputs based on the configuration and requirements of the application.
The UHD-SDI wrapper has a cpllreset_in input which should be driven by either the rx_pll_reset_out or the tx_pll_reset_out or some logical combination of those two to reset the CPLL. The GTX common wrapper has a qpllreset_in port which should be driven by a rx_pll_reset_out or tx_pll_reset_out (or combination thereof) of one or more UHD-SDI wrappers in the same Quad as the GTX common. Usually one UHD-SDI wrapper per Quad is designated as the QPLL master and is responsible for resetting the QPLL in that Quad.
As an example, all four transceivers in a GTX Quad are used for SDI. The RX units only use the QPLL, and the TX units are dynamically switched between QPLL and CPLL (the configuration shown in Figure 1). In this configuration, the following reset connections could be used. The tx_pll_reset_out port of each UHD-SDI wrapper is connected to the cpllreset_in port of that same UHD-SDI wrapper. The rx_pll_reset_out port of one of the UHD-SDI wrappers is connected to the qpllreset_in port of the GTX common and that UHD-SDI wrapper is considered to be the QPLL master and is responsible for resetting the QPLL. The qplllock_out port of the GTX common must be connected to the qplllock_in port of every UHD-SDI wrapper in that Quad. The cplllock_out port of the UHD-SDI wrapper is a status indicator only and does not need to be connected to anything for proper operation.