The LogiCORE IP SMPTE UHD-SDI core (called the UHD-SDI core in the rest of this document) can be connected to a GTX transceiver in a 7 series FPGA to implement an SDI interface capable of supporting the SMPTE SD-SDI, HD-SDI, 3G-SDI, 6G-SDI, and 12G-SDI standards. The UHD-SDI core and GTX transceiver must be supplemented with some additional logic to connect them together and implement a fully functional UHD-SDI interface. This application note describes this additional control and interface logic and provides necessary control and interface modules in Verilog source code.
In this application note, the term SDI is used to generically refer to the SMPTE family of interfaces standards including SD-SDI, HD-SDI, 3G-SDI, 6G-SDI and 12G-SDI. 7 series GTX transceivers can support all SDI bit rates up to and including 12G-SDI. Rates up to 6G-SDI can be supported with the GTX transceivers in -1 speed grade devices. However, 12G-SDI bit rates are only supported with the GTX transceivers in -3 speed grade devices and only in certain packages due to line rate limitations of the GTX transceivers. Refer to Kintex 7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS182) and Virtex 7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS183) for the maximum line rates supported by the GTX transceivers for each combination of speed grade and device package. The primary functions of the device-specific SDI control logic provided with this application note are:
- Reset logic for the GTX transceiver
- Dynamic switching of the GTX RX and TX serial clock dividers to support the five SDI standards
- Dynamic RX and TX reference clock switching to support two different bit rates in
each of the HD-SDI, 3G-SDI, 6G-SDI, and 12G-SDI standards
- 1.485 Gb/s and 1.485/1.001 Gb/s in HD-DI mode
- 2.97 Gb/s and 2.97/1.001 Gb/s in 3G-SDI mode
- 5.94 Gb/s and 5.94/1.001 Gb/s in 6G-SDI mode
- 11.88 Gb/s and 11.88/1.001 Gb/s in 12G-SDI mode
- Dynamic switching of the GTX RXDATA and TXDATA port widths
- 20-bit RXDATA and TXDATA ports for SD-SDI, HD-SDI, and 3G-SDI modes
- 40-bit RXDATA and TXDATA ports for 6G-SDI and 12G-SDI modes
- Data recovery unit for recovering data in SD-SDI mode
- RX bit rate detection to determine if the RX is receiving integer frame-rate signals (line rates such as 1.485 Gb/s and 2.97 Gb/s) or fractional frame-rate signals (line rates such as 1.485/1.001 Gb/s and 2.97/1.001 Gb/s)
Also supplied with this application note is a wrapper file that contains a GTX transceiver instance, an instance of the control module, and an instance of the SMPTE UHD-SDI core with the necessary connections between them. This file simplifies the process of creating an SDI interface.
This application note includes an example SDI design using the UHD-SDI core. This example design runs on the KC705 evaluation board. A Fidus 12G-SDI FPGA mezzanine card (FMC) is also required to provide the UHD-SDI physical interfaces.
In this document, the following terms are used. The UHD-SDI core refers to the SMPTE UHD-SDI core that is available in the AMD Vivado™ IP catalog starting with the 2015.1 release. The control module is a module that implements the various device-specific functions when using the GTX to implement an UHD-SDI interface using the UHD-SDI core. The control module is supplied on source code form with this application note. The GTX wrapper is a wrapper file for a single GTX transceiver generated by the 7 Series FPGAs Transceivers Wizard that is available in the IP catalog. The GTX common wrapper is a wrapper file containing the QPLL for the GTX Quad also generated by the 7 Series FPGAs Transceivers Wizard when the GTX wrapper is generated. The SDI wrapper is a wrapper module that instances and interconnects the SMPTE UHD-SDI core, the GTX wrapper, and the control module. The SDI wrapper is supplied in source code form with this application note. The GTX common wrapper is not included in the SDI wrapper and must be instantiated separately in the application. The following figure is a simplified block diagram of how the various pieces fit together to form an UHD-SDI interface.