Immediately following FPGA configuration, the SDI control module performs initialization sequences for the QPLL, the CPLLs, and the RX and TX units of the GTX transceiver. The control module has separate controllers for the RX and the TX. These controllers perform the following initialization sequence. The sequence described here is for the RX. The TX initialization sequence is identical except that it uses TX ports rather than the RX ports described.
- After waiting at least 500 ns following completion of FPGA configuration, assert the PLL reset and gtrxreset signals.
- Wait until the rx_refclk_stable input is asserted, then negate the PLL reset.
- Wait until the PLL lock signal is asserted, then negate the gtrxreset signal.
- Wait until the rxresetdone signal is asserted, then indicate that the initialization sequence is complete.
Also, the GTX txuserrdy and rxuserrdy inputs must be properly controlled. The SDI wrapper generates both of these signals. It asserts txuserrdy after gttxreset is negated. Likewise, it asserts rxuserrdy after gtrxreset is negated. In step 2, step 3, and step 4 of the initialization sequence where the sequence is waiting on a condition to be satisfied, a timeout counter is running. If the timeout counter expires before the wait condition is satisfied, the state machine moves to a timeout state where it increments a retry counter and then cycles back in the initialization sequence and resumes the sequence. If the retry counter reaches its maximum count due to numerous timeouts, the initialization sequence fails and the state machine moves to a fail state, indicating failure of the initialization sequence.