There are three conditions that require the TX portion of the GTX transceiver to be reset:
- Whenever the PLL that supplies the serial clock to the GTX TX is reset, the gttxreset port must be used to reset the TX section. This is done automatically after FPGA configuration by the SDI control module and whenever the user application asserts the tx_gtx_full_reset_in to the SDI wrapper, causing both the PLL and the GTX TX to be reset.
- The SDI control logic automatically resets the GTX TX using the gttxreset input whenever txsysclksel port is changed dynamically. The txsysclksel port is used to select between the QPLL and the CPLL as the serial clock source for the GTX TX. Each GTX transceiver has its own txsysclksel port and can independently switch its serial clock source between the two PLLs. The txsyclksel port should not be controlled directly by the application. The SDI control module dynamically changes the txsysclksel port of the GTX transceiver in response to changes on its tx_pll_select_in input. When the control module detects a change on its tx_pll_select_in input, it first asserts the gttxreset signal, then changes txsysclksel, and then negates gttxreset. The sequence is complete after the GTX transceiver asserts its txresetdone output. At that point, the SDI control module indicates completion of the txsysclksel change by asserting its tx_change_done_out output.
- The SDI control logic automatically resets the GTX TX using the gttxreset port whenever the PLL divider in the GTX TX is changed by the SDI control logic through the DRP in response to a change on the tx_mode_in input port. As with changes of the txsysclksel port, the SDI control logic indicates completion of this reset by the tx_change_done_out output.
The UHD-SDI wrapper has three reset inputs for the TX section:
- tx_rst_in
- When asserted High, this input resets the SDI TX datapath in the UHD-SDI core. It does not reset the GTX at all.
- tx_gtx_full_rest_in
- When asserted High, this input resets both the PLL associated with the TX and then the TX section of the GTX transceiver (gttxreset). These two resets are sequenced so that the gttxreset does not complete until after the PLL reset is complete and the PLL is locked to its reference clock.
- tx_gtx_reset_in
- When asserted High, this input resets only the TX section of the GTX transceiver (gttxreset). If the PLL is not locked when the gttxreset sequence begins, the gttxrest sequence does not complete until after the PLL is locked.