FPGA Resource Usage - FPGA Resource Usage - XAPP1249

The following table shows the FPGA resources required for a UHD-SDI interface with a 7 series GTX transceiver. The resource usage includes all the modules required to implement the interface included in one SDI wrapper instance. Resource usage is shown for various common configurations.

The results shown were achieved with the Vivado tools 2018.1. The SDI receiver and transmitter interface designs do not use any MMCM clock managers.

Typically, one global or regional clock is required for each SDI TX and for each SDI RX. In addition, one fixed frequency global clock is required for timing purposes in the SDI wrapper. This fixed frequency clock is usually also used as the GTX DRP clock. Only one such fixed frequency global clock is required no matter how many SDI interfaces are implemented in the FPGA.