Both the BBRAM and eFUSE 256-bit symmetric keys are loaded via the external JTAG using the Vivado Hardware Manager (see the Key Agility (Response) section on how the internal MASTER_JTAG port can be used to update the BBRAM key). For UltraScale and UltraScale+ FPGAs, this key loading path is write-only to the device. There is no physical datapath to read back either key. (In previous families the key was protected by protocol during the loading process where upon entering “key access mode” the existing key and configuration memory were immediately cleared before a new key could be written and then read back to check integrity.) When a key is written to the device via JTAG, a key integrity check is started by writing the expected CRC32 value via JTAG to the device. An actual CRC32 integrity check is calculated on the stored key by the device (internally) and compared to the expected CRC32 that was just received via the JTAG port. A pass/fail type of result is then written out by the device to the JTAG port instead of the actual key data to signify integrity status. Removing the physical readback path for the key increases the security of the stored key.
Note: For BBRAM-based keys, prior to writing the key, the existing
key in BBRAM is zeroized (erased and verified).