Unique Identifiers (Detection) - Unique Identifiers (Detection) - XAPP1098

Developing Tamper-Resistant Designs with UltraScale and UltraScale+ FPGAs (XAPP1098)
Document ID
XAPP1098
Release Date
2025-05-22
Revision
1.5.1 English

Two types of unique identifiers (UIs) are available for use: device DNA and user eFUSE. These UIs can be used as anti-cloning security measures (for instance, someone steals the user’s bitstream and uses it to program their own devices) or for enabling or disabling certain features (upgrade or downgrade) depending on the value of the UI.

Device DNA consists of a 96-bit device-specific serial number and is set by AMD in one-time programmable (OTP) eFUSE bits on the FPGA during the manufacturing flow (FPGA logic read access to the value is via the DNA_PORTE2 primitive, or it can be read externally via JTAG). User eFUSE provides 32 bits of user read/write OTP area and is set by the user via JTAG (FPGA logic read access to the value is via the EFUSE_USR primitive). Both of these UIs can be used separately or in conjunction for security purposes.

Note: Use of device DNA or user eFUSE provides for unique IDs, but does not provide cryptographically strong confidentiality or authentication (such as AES-GCM). AES-GCM encryption is the preferred method of providing anti-cloning protection. However, by taking advantage of these UIs, you can add another layer to the overall AT scheme.

These UIs can be used to link the bitstream to one particular device (in the case of device DNA, or multiple devices in the case of user eFUSE). The UI comparison is put into the FPGA design by the user and the results of this comparison can be used to gate FPGA activity. For example, if the UI comparison fails, the design can refuse to function or function with limited capability. An example use case of the UIs is as follows:

  1. Setup: Read the UI value(s) from the FPGA via JTAG, generate a hash from the UI value(s), and store in a flash device accessible to the FPGA using a robust one-way function (a keyed type is the most secure) as shown in the following figure.
    Figure 1. Encrypt the DNA Value with a Confidential Key
    x1098_08 Sheet.13 Key Key Sheet.14 Stored Hash (Flash) Stored Hash(Flash) Sheet.15 X1098_08_061115 X1098_08_061115 Sheet.16 One-Way Function One-WayFunction Sheet.23 JTAG JTAG Sheet.24 UI UI Standard Arrow.589 Standard Arrow.591 Standard Arrow.589.31
    The key for the one-way function shown in the following figure could be stored within the encrypted bitstream. If bitstream encryption is not used, this approach relies on the complexity of the bitstream to keep the key confidential.
  2. Configure the FPGA.
  3. Compare: The FPGA design reads the UI value from either or both the DNA_PORT and EFUSE_USR primitive(s) and then calculates the checksum using the same algorithm. The design then compares the calculated hash with the hash read from flash. If the hash passes, the design is allowed to become active.
    Figure 2. Hash Comparison
    x1098_09 Sheet.23 Key Key Sheet.24 Hash Hash Sheet.25 X1098_09_061115 X1098_09_061115 Sheet.26 One-Way Function One-WayFunction Sheet.28 Flash Flash Sheet.29 FPGA FPGA Sheet.30 Stored Checksum Stored Checksum Sheet.31 Sheet.38 UI Port UI Port Sheet.39 Sheet.40 = = Sheet.41 Standard Arrow.589 Sheet.46 Standard Arrow.589.47 Standard Arrow.591 Standard Arrow.589.51
    For additional information on these UIs, consult the UltraScale Architecture Configuration User Guide (UG570). Security Solutions Using Spartan-3 Generation FPGAs (WP266) also talks about device DNA operation for the AMD Spartan™ -3 generation FPGAs.