Revision History - Revision History - XAPP1098

Developing Tamper-Resistant Designs with UltraScale and UltraScale+ FPGAs (XAPP1098)

Document ID: XAPP1098
Release Date: 2025-05-22
Revision: 1.5.1 English

The following table shows the revision history for this document.

Section	Revision Summary
05/22/2025 Version 1.5.1
General update	Editorial updates only. No technical content updates.
08/01/2024 Version 1.5
Summary	Updated link to FPGA product page. Updated link to Vivado Design Suite page.
Volatile and Non-Volatile Key Storage	Removed link to Introduction to Indirect Programming -SPI or BPI Flash Memory. Added links to UG908 and Answer Record 73459.
Bitstream Authentication (Asymmetric)	Added important note. Removed "Authentication of unencrypted bitstreams" from list of RSA asymmetric authentication use cases. Updated Figure 2.
DPA Solution Comparison	Updated link to the DPA content website.
Unique Identifiers (Detection)	Updated Figure 1 and Figure 2
Load CT Only When Needed (Prevention)	Updated Figure 1 and Figure 2.
Restricting Access to FPGA Probe Points	Removed link XTP301.
03/25/2021 Version 1.4
Added a note about not reusing the keys across SSI technology devices. Updated bitstream format diagram to indicate that encryption is optional.
09/14/2018 Version 1.3
Updated bitstream authentication, JTAG port permanent disable, and bitstream decryptor permanent disable rows, and added row for internal test scan permanent disable in Table 1. Replaced “obfuscating key” with “family key,” and added note about obtaining family key in Obfuscated Key Loading and Storage. Replaced RSA_AUTH_ALL_EFUSE with RSA_AUTH. Added Internal Test Scan Disable (Passive) in Bitstream Authentication (Asymmetric). Added UltraRAM to first paragraph in Configuration Memory Clearing (Response/Penalty).
02/22/2017 Version 1.2
Initial Xilinx release.