The UltraScale and UltraScale+ FPGAs include a new 128-bit USER eFUSE register. This register can be used to flexibly meet your needs for a non-volatile area. The eFUSE register bits can only be programmed and read back using JTAG instructions (see the UltraScale Architecture Configuration User Guide (UG570) for more information). These eFUSE bits can be programmed via the external JTAG port or the internal MASTER_JTAG. Contact your local AMD FAE for additional details on how to program eFUSE bits from within the device via MASTER_JTAG.
Important: After these eFUSE bits are programmed, it
is possible to program another eFUSE (a write disable) that prevents any more
programming of the eFUSE register bits (to “lock the door”). Thus, an adversary
cannot attempt to overwrite the tamper log information.