Critical data or sensitive parameters can be stored in FPGA logic registers such as a user key (not the AES BBRAM bitstream decryption key). Asserting the GSR input on the STARTUP block in response to a tamper event causes all FPGA registers (flip-flops) to be restored to their default state. This could be an immediate step to take along with KEYCLEARB to make sure all sensitive data in the FPGA is erased as soon as possible. The GSR does not impact the shift register look-up table (SRL) or block RAM contents. These must be cleared by your design or by an IPROG command.