Depending on the system design, critical (red) information might flow out of the external FPGA pins (for example, a cryptographic module). Asserting the GTS input on the STARTUPE3 block in response to a tamper event causes all FPGA outputs to immediately enter a high-Z state and prevent any more data from flowing outside the FPGA. This could be an immediate step to take just prior to an IPROG or KEYCLEARB to make sure red data flow is halted as soon as possible.