DPA Solution Comparison - DPA Solution Comparison - XAPP1098

Developing Tamper-Resistant Designs with UltraScale and UltraScale+ FPGAs (XAPP1098)

Document ID
XAPP1098
Release Date
2025-05-22
Revision
1.5.1 English

Only one of the two random data countermeasures (configuration counting or authenticate-then-decrypt) can be enabled on an UltraScale or UltraScale+ FPGA at any one time, so you should understand the trade-offs with each method. Key rolling must always be used with either one of these methods to ensure that a complete set of DPA countermeasures are being used. The following table summarizes the trade-offs.

Table 1. Comparison of Trade-offs in Configuration Counting and Authenticate-then-Decrypt
Metric Configuration Counting Authenticate-then-Decrypt
Supported key storage BBRAM BBRAM and eFUSE
Minimum data exposed per key 1 4 blocks

246 blocks (UltraScale FPGAs)/

186 blocks (UltraScale+ FPGAs)

Increases bitstream size Yes No
Increases configuration time Based on key life Based on configuration mode
Requires eFUSE programming No Yes 2
Supports all bitstream features (compression, PR, tandem) Yes No
Field key maintenance Yes No
  1. Refer to https://dpacontest.telecom-paris.fr/home/ for the current state of the art in open-literature DPA attacks.
  2. Required for the hash of the RSA public key.