Corruption of any of the internal configuration memory cells (which are configured by the decrypted bitstream) could cause the FPGA to operate in an unknown or undesired manner. The corruption could occur by an intentional post configuration tamper attack or by an unintentional event such as a single-event upset (SEU). By using the SEM IP core (refer to Soft Error Mitigation (SEM) Core), continuous readback of configuration data in the background of a design is performed to detect any bit flips. The SEM IP core can also perform SEU corrections.