Storing an encrypted bitstream in external flash (or other means) and then decrypting it during FPGA configuration (via the FPGA’s internal decryption engine) provides for a very high level of confidentiality. This ensures that information contained in the bitstream is only accessible to those who share the same (symmetric) secret key. Bitstream encryption and decryption provides confidentiality while the system is at rest and during configuration. It protects the FPGA design contents, including block RAM and flip-flop initialization data. AMD highly recommends that the externally stored bitstream always be in encrypted form.
To take advantage of this security feature, the configuration bitstream must first be encrypted by the Vivado software using the write_bitstream Tcl command and the appropriate properties that must be defined in the XDC file. See the AMD Vivado Design Suite, UltraScale Architecture Configuration User Guide (UG570), and Vivado Design Suite User Guide: Programming and Debugging (UG908) for more details. The Vivado software uses a key supplied by the user to perform the encryption. If an AES key is not supplied, the Vivado software optionally generates one automatically. However, keys generated by the Vivado software are pseudorandom. Truly random keys are more secure. The key is then loaded into the FPGA via the JTAG port using the Vivado hardware manager.
When bitstream decryption is enabled on UltraScale and UltraScale+ FPGAs (and asymmetric RSA-2048 authentication is not enabled via eFUSE), symmetric authentication is automatically enabled because AES-GCM is an authenticated encryption and decryption algorithm. AES-GCM combines the counter mode for confidentiality with an authentication mechanism that is based on a universal hash (authentication tag) function. Therefore, AES-GCM provides not only confidentiality but integrity and authentication at the same time. This cryptographically strong authentication scheme ensures that any attempt at modifying the bitstream (even just a single bit) drastically alters the bitstream’s signature, thus preventing the device from starting up. Basically, symmetric authentication guarantees the source is genuine—only the person that was authorized to configure the device can succeed in doing so.
If the authentication check passes, the device then begins normal operation (the startup commands take place). Evidence of the authentication step failing is the absence of the DONE output signal asserting High after the bitstream is loaded, the INIT_B signal asserting Low, and the HMAC_ERROR bit in the STATUS configuration register asserting High. An authentication failure might indicate that the bitstream has been tampered with. It could also indicate that the channel used for bitstream loading is noisy and bit corruption(s) are taking place during the configuration process.
Additionally, AES-GCM was designed to facilitate high-throughput hardware implementations. The AES-GCM decryptor in UltraScale and UltraScale+ FPGAs can accept encrypted bitstreams in 32-bit wide format (previous families were limited to 8-bit wide format). This allows for near parity in the device configuration time between unencrypted and encrypted bitstreams.