The active AT features require you to do something in your FPGA logic design to take advantage of the particular features. For example, you must instantiate the STARTUP primitive in your design to drive the KEYCLEARB input in response to some tamper event. The following table summarizes each of these active features, their use cases, and how you can implement the feature.
| Feature | Use Case | User How-To |
|---|---|---|
| JTAG port permanent disable (eFUSE) 1 | Permanently prevent unauthorized JTAG access in response to a tamper event. | Instantiate the MASTER_JTAG primitive or internally program the DISABLE_JTAG eFUSE (permanent disable). This also requires forcing authentication (symmetric with aes_efuse_only or symmetric with rsa_auth_all). |
| JTAG port temporary disable | Prevent an unauthorized JTAG access. |
Instantiate the MASTER_JTAG primitive or instantiate the BSCANE2 primitive with the DISABLE_JTAG attribute set to TRUE, or use the BITSTREAM.GENERAL.DISABLE_ JTAG option. |
| JTAG port monitor | Detect unauthorized JTAG access. | Instantiate the BSCANE2 primitive and add a monitoring/response function in the FPGA logic. If MASTER_JTAG is used, you will be detecting activity on the internal JTAG port. |
| Configuration memory integrity checking | In-the-background check of configuration memory integrity (non-interfering runtime check). | Instantiate the soft error mitigation (SEM) IP core. Refer to Soft Error Mitigation (SEM) Core for more information. |
| Unique identifiers (device DNA and user eFUSE) | Prevent the design from operating (or operate in a limited manner) if unique identifier is not recognized. | Develop FPGA logic to be able to read and process the unique identifier(s) and determine if they are valid. |
| On-chip temperature and voltage monitor/alarms | Ensure device is operating within normal environmental limits. | Instantiate the system monitor (SYSMONE1) primitive and develop FPGA logic to check and respond to environment status. |
| Uninterruptible internal clock source | Ensure active AT functions cannot be disabled by simply removing an external clock source. | Instantiate STARTUPE3 primitive, connect to the CFGMCLK output, and use that as the clock source for user-defined AT functions. Bitstream encryption must also be used to prevent the clock from being turned off. |
| External PROGRAM_B intercept | Hold off device configuration to allow data elements that cannot be reset to be cleared (for example, elements that are not automatically cleared by house-cleaning prior to configuration such as transceiver FIFOs). | Instantiate STARTUPE3 primitive and develop FPGA logic to determine the proper conditions for PROG_ACK assertion after receiving a PROG_REQ. |
| Configuration memory clearing | Erase the configuration memory in response to a tamper event. | Instantiate ICAPE3 primitive and develop FPGA logic to determine the proper conditions for sending an IPROG command. |
| Key agility (BBRAM only) 1 | Update the BBRAM key securely in the field without having to return the board or module to a secure facility. | Instantiate the MASTER_JTAG primitive along with logic that can perform a secure key exchange in FPGA logic in response to a key management event. |
|
BBRAM key zeroize (erase + verify) 1 |
Zeroize the battery-backed key in response to a tamper event. | Instantiate STARTUPE3 primitive and develop FPGA logic to determine the proper conditions for KEYCLEARB assertion and for reading the verification bit in the STATUS register. |
| Non-volatile (eFUSE) tamper event logging 1 | Securely log a tamper event in non-volatile memory (eFUSE) for later forensic analysis. | Instantiate the MASTER_JTAG primitive and develop FPGA logic function for logging tamper events in eFUSE bits (POST_CRC must be paused when eFUSE bits are programmed). |
| Bitstream decryptor permanent disable (eFUSE) 1 | Permanently prevent side-channel analysis of the bitstream decryptor (either as a preventive measure or in response to a tamper event). | Instantiate the MASTER_JTAG primitive and develop FPGA logic to program the decryptor disable eFUSE. |
| GTS | Shut off outputs in response to a tamper event to prevent any information leakage out of the device. | Instantiate STARTUPE3 primitive and develop FPGA logic to determine the proper conditions for GTS assertion. |
| GSR | Restore user flip-flop states to initial conditions in response to a tamper event, effectively clearing possible CT from within the device. | Instantiate STARTUPE3 primitive and develop FPGA logic to determine the proper conditions for GSR assertion. |
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