Developing Tamper-Resistant Designs with UltraScale and UltraScale+ FPGAs (XAPP1098)

Document ID: XAPP1098
Release Date: 2024-08-01
Revision: 1.5 English

Summary
Introduction
Passive AT Silicon Features
Bitstream Confidentiality and Authentication (Symmetric)
Volatile and Non-Volatile Key Storage
Write-only Key Load with Integrity Check
Obfuscated Key Loading and Storage
Bitstream Authentication (Asymmetric)
DPA Protections
Invalid/Random Bitstream Data
Configuration Counting Trade-off
Authenticate-then-Decrypt Trade-off
Valid Bitstream Data
DPA Solution Comparison
Hardened Readback Disabling Circuitry
Internal Test Scan Disable (Passive)
JTAG Port Disable (Passive)
Active AT Silicon Features
JTAG Port Disable (Active)
JTAG Monitoring (Detection)
Configuration Memory Integrity Checking (Detection)
Unique Identifiers (Detection)
On-Chip Temperature and Voltage Monitors/Alarms (Detection/Response)
Uninterruptible Internal Clock Source (Detection)
External PROGRAM_B Intercept (Prevention and Detection)
Configuration Memory Clearing (Response/Penalty)
Key Agility (Response)
BBRAM Key Zeroize (Response/Penalty)
Non-Volatile (eFUSE) Tamper Event Logging (Response)
Bitstream Decryptor Permanent (eFUSE) Disable (Prevention/Response/Penalty)
Global 3-State (Response/Penalty)
Global Reset (Response/Penalty)
Tamper Resistance Guidance
Load CT Only When Needed (Prevention)
Key Erase via External Shunt
Preemptive BBRAM Key Zeroize
Avoiding Weak or Duplicate Keys
Sending Tamper Status Outputs to System
Restricting Access to FPGA Probe Points
Conclusion
References
Revision History
Please Read: Important Legal Notices

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