It is standard practice to require an LPM function capable of handling several million prefixes or rules. AMD has developed intellectual property that allows a 64-byte location in DRAM to accommodate between one and eight prefixes. Consequently, a table comprising 1 M prefixes can be comfortably stored using 512 K 64-byte entries in DRAM. This solution offers significant flexibility.
For example, this design supports IPv4 and IPv6 prefixes. It accommodates all 128 IPv6 prefixes and allocates at least 72 bits of additional fields in the key for exact match operations. The system demands an average of 1.1 64-byte DRAM reads per search, enabling a typical LPDDR5 device—featuring two 16-bit LPDDR5-6400 channels—to achieve search rates up to approximately 180 MS/s.
The following specifications and corresponding resource counts describe the FPGA resource requirements for this IP:
- Specifications
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- Up to 1 M prefix rules stored in a 32 MB DRAM buffer
- Using LPDDR5-6400 2 x 16-bit channels
- Key width: 160 bits; Response width: 32 bits
- Maximum clock frequency: 375 MHz
- Target search rate: 150 MS/s
- FPGA resource count
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- 33,000 LUTs
- 72 UltraRAMs