Faster DRAM Interfaces are Emerging - Faster DRAM Interfaces are Emerging - WP570

Advances in High-Capacity Algorithmic CAMs on AMD Versal Devices (WP570)
Document ID
WP570
Release Date
2026-05-01
Revision
1.0 English

Random reads to DRAM are typical in CAM applications and historically, they result in relatively low bandwidth efficiency. Comparing DDR4 and LPDDR5 SDRAM reveals significant improvements in random read performance. Key constraints used for this comparison include the following:

  • This evaluation measures performance for 64-byte/64-byte aligned read transactions, consistent with typical 64-byte CAM entries.
  • Use of Versal architecture hard memory controllers.
  • ECC protection using 72-bit DDR4 or inline ECC for LPDDR5.

The following table demonstrates that random read bandwidth per pin has increased over three times.

Table 1. Random Read Rate per Pin (DDR4 vs. LPDDR5)
DRAM Type DDR4 LPDDR5 Units
Interface data width 72 16 bits
Interface rate 2400 6400 Mb/s
Interface size 135 36 pins
DRAM bank count 8 16 banks
Peak 64-byte read rate 300 200 M/s
Random read efficiency 40 50 %
Effective 64-byte random read rate 120 100 M/s
Effective 64-byte random read rate per pin 0.89 2.77 M/s
Note: While LPDDR5 random read efficiency is close to 80%, a value of 50% is used in this table to account for the overhead caused by inline ECC. This is necessary in the comparison because the comparison uses a 72-bit DDR4 interface with ECC capability. Inline ECC reduces bandwidth because it stores parity bits in the same memory space the data, so the controller must issue extra read and write commands on the data bus to access those codes.
Note: This comparison uses conservative interface rates, instead of choosing DDR4 3200 or LPDDR5X 8533 M as the maximum rate supported by Versal devices. With a conservative PCB design mindset, it was observed that designers normally choose to target 2400 for DDR4. Thus, it was decided to use 6400 as the LPDDR5 rate in this comparison. Using a 8533-M LPDDR5X rate predicts a 15% yield improvement in 64-byte random read rate over 6400.

The performance gains stem from several key factors:

  • Higher interface signaling rates—DDR4 at 2400 Mb/s and LPDDR5 at 6400 Mb/s.
  • Improved random-access efficiency—DDR4 at 40%, LPDDR5 at 50%, aided by narrower 16-bit interfaces and more banks (16 banks versus DDR4 8 banks).
  • LPDDR5 boosts bandwidth by multiplexing control and address signals over multiple clock cycles.