Tile-Based Rendering GPU - Tile-Based Rendering GPU - WP557

Decoding the Versal AI Edge Series Gen 2 and Prime Series Gen 2 GPU for Next-Gen Visualization (WP557)

Document ID
WP557
Release Date
2025-01-03
Revision
1.0 English

The Mali-G78AE GPU rendering takes a different approach than traditional immediate mode rendering, commonly called tile-based rendering, designed to minimize the amount of power-hungry external memory accesses that are needed during rendering. Instead of rendering objects immediately, the frame buffers are broken down into rectangular tiles that are then processed one at a time. The GPUs break up the screen into small 16 x 16 pixel tiles and construct a list of the rendering primitives that are present in each tile. When the GPU fragment shading step runs, each shader core processes one 16 x 16 pixel tile at a time, rendering it to completion before starting the next one. By only rendering the area within the current tile, this area can be processed in fast on-GPU memory. The tile then gets written out to main memory only when rendering is finished, so memory only gets touched once. Because a 16 x 16 tile is only a small fraction of the total screen area, it is possible to keep the entire working set (color, depth, and stencil) for a whole tile in a fast RAM, which is tightly coupled with the GPU shader core.

This tile-based approach has several advantages. They are mostly transparent to the developer but worth knowing about when trying to understand bandwidth costs of your content:

  • All accesses to the working set are local, and are both fast and low power.
  • Blending is both fast and power-efficient, because the destination color data required for many blend equations is readily available.
  • A tile is sufficiently small that enough samples can be stored locally in the tile memory to allow 4x, 8x, and 16x multisampling anti-aliasing (MSAA).
  • The GPU only has to write the color data for a single tile back to memory at the end of the tile, where its final state is known.
  • A typical pipe-lining approach for graphics in tile-based deferred rendering (TBDR) systems involves a two-stage process. First, the geometry is shaded, followed by the fragment stage, which finalizes the render pass. The vertex processing and tiling for multiple render passes are completed in advance, ensuring the fragment stage consistently has tasks to process without delays.
Figure 1. Hardware Data Flow and Memory Interactions