Resource Utilization

Simplify Packet Processing Design with P4 and Vivado Tools (WP555)

Document ID
WP555
Release Date
2024-01-24
Revision
1.0 English

Very complex parsers can be supported in VNP4, while still operating at 200 Gb/s line rate and 300 million packets per second. To illustrate this point, a consolidated switch P4 example was taken and ported to the VNP4 XSA target, with the match-action section removed to focus on the parser. This example has 130,000 unique paths through the P4 parser (including error conditions), and it uses 31k LUTs. The example showcases the level of complexity in terms of parsing that can be enabled by VNP4. While a robust example, it is not the limit of the parsing complexity that can be supported in VNP4.

Figure 1. Parse Graph for consolidated_switch_xsa.p4

For comparison, the parse graph of the less complicated FiveTuple example design available within the tool.

Figure 2. Parse Graph for FiveTuple.p4

Typically, the CAMs have a much larger utilization than the packet parsing and editing functions, along with other parts of the logic design outside VNP4, therefore designers can focus their efforts on system level trade-offs such as table entry numbers. Some other examples of resource utilization are given in the following section.