Programming Protocol-independent Packet Processing

Simplify Packet Processing Design with P4 and Vivado Tools (WP555)

Document ID
WP555
Release Date
2024-01-24
Revision
1.0 English

An industry standard, domain specific language, programming protocol-independent packet processors (P4), is used for requirements capture. VNP4 converts the P4 design intent into an AMD FPGA or adaptive SoC design solution and allows programmers to build new data planes by explicitly specifying the header and packet processing requirements. To implement a P4 design, the compiler maps the intended functionality onto a custom data plane architecture of VNP4 RTL engines and software drivers. This mapping chooses appropriate engine types and customizes each of them based on the P4-specified processing. The specialized engines used to achieve this goal include parsing engines, match-action engines, and deparsing engines, each generated according to an application-specific requirement.

The generated RTL is integrated in a packaged IP in the AMD Vivado™ Design Suite where it can immediately be combined with other standard IPs, such as media access controllers, to create a complete device design. The design is then synthesized and a bit-file is generated for the targeted device. Even before synthesis design data is generated, critical design metrics are available, such as required latency and memory resources.

The current AMD solution was designed based upon feedback from hundreds of customers and information gathered from earlier iterations. The three key elements that differentiate this latest generation of the tool are:

  • Native support for the P416 language
  • Algorithmic content addressable memory technology
  • Dedication to efficient resource utilization and robust timing closure