Simplify Packet Processing Design with P4 and Vivado Tools (WP555)

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VNP4 allows for easy migration in several ways. Migrating to a different line rate is straightforward (for example, 100 Gb/s to 200 Gb/s), by scaling clock frequencies and bus widths in the GUI. No changes are required to the P4 code, and confidence can be maintained that the original implementation of the requirements remains faithful to the design intent. This can be very effective if developing a family of products with each family member targeting a specific line rate. The same P4 code generates the packet processing RTL in each family member, saving time.

Prototyping with smaller table implementations before moving to a larger number of table entries is also trivial to enable even more rapid prototyping through to hardware implementation. This can include starting off with on-chip SRAM before later increasing the size of the same P4 table to target off-chip DRAM. In a pure RTL design flow, this can be time consuming and introduce new risks. Any impact to the latency or performance of one table can have consequential impact on other parts of the P4 pipeline, for the whole design to remain in sync. However, VNP4 automatically manages all these latency and alignment challenges. More extensive changes in design are also enabled in cases where evolving functionality and requirements are supported through small P4 updates.