Introduction

Simplify Packet Processing Design with P4 and Vivado Tools (WP555)

Document ID
WP555
Release Date
2024-01-24
Revision
1.0 English

The benefits of VNP4 fall broadly into two categories; reduced engineering effort and high quality, performant results.

Figure 1. VNP4 Benefits

Productivity
The solution reduces development effort.
Rapid Prototyping and Time to Market
Getting your product to market is faster with the accelerated design cycle. Iterating through multiple design options is simple and quick.
Features
Extensive features differentiate your product, including options in User Metadata and User Externs.
Migration
The design intent can be migrated from one FPGA or SoC to another.
Expansion
Packet-processing blocks generated by VNP4 can be deployed in parallel or serially to support capabilities such as multi-level parsing and multi-data-pipeline systems.
Domain Specificity
This high-level abstraction solution is domain specific, allowing you to take advantage of abstraction without sacrificing performance.
FPGA Expertise for Packet Processing
The solution and quality of hardware implementation reflects years of experience in high-speed FPGA design and memory subsystems for high throughput packet processing.
Performance
The system has been engineered from the ground up to ensure high throughput, low latency, and minimized resource utilization.