Abstract

Simplify Packet Processing Design with P4 and Vivado Tools (WP555)

Document ID
WP555
Release Date
2024-01-24
Revision
1.0 English

The AMD Vitis™ Networking P4 tool (VNP4) is a high-level design environment used to simplify the design of packet-processing data planes that target FPGAs and adaptive SoCs. It converts designs coded in P4—the ubiquitous network programming language—into device-ready RTL code for optimal hardware implementation. By using this tool, you can significantly reduce engineering effort required to develop device-based packet-processing systems, while still achieving high quality results in terms of performance per LUT or performance per RAM. The benefits of designing with VNP4 are outlined in this document.