For each entry in the percentage of design columns, there is a related entry of the raw FIT for the logic used to implement the function.
Usually, raw FIT can only be calculated after the IP is implemented in silicon, which is after the design is completely verified. In the case of IP where the deliverable is a design package and not a hardware component, the designer does not know the device libraries or the raw FIT for each of these functions until after synthesis and layout.
Figure 1. Architecture Updated with Diagnostic Block
