MM2S Block

Replacing FMEA with Datapath Analysis for IP Designs (WP545)
Document ID
WP545
Release Date
2023-06-14
Revision
1.0 English
The following table lists the external connections and internal signaling for the MM2S block.
Table 1. MM2S Block
Block 1 MM2S Block ID TAG Fault Modes Fault Initiators Proposed Diagnostics Repeat Claimed DC Coverage Primary Function- Percent of Design Diagnostic - Percent of Design
External Connections Signal/Bus Name
1 m_axi_mm2s_ TOP_axi_master Bus Write to incorrect address Address Write register corruption Parity   99.50% 3.00%
Control plane state machine corruption Redundancy   99.80%  
Clocking corruption      
Driver/receiver failure      
Bus Write with incorrect data Write data register corruption Parity   99.50%  
Control plane state machine corruption Redundancy   99.80%  
Clocking corruption      
Driver/receiver failure Loopback   90.00%  
Bus Read from incorrect address Read address register corruption Parity   99.50%  
Control plane state machine corruption Redundancy   99.80%  
Clocking corruption      
Receiver failure      
Bus read incorrect data Read data register corruption Parity   99.50%  
Control plane state machine corruption Redundancy   99.80%  
Clocking corruption      
Receiver failure Parity   99.50%  
1 (cont'd)     Bus Hang Control plane state machine corruption Redundancy   99.80%  
  External watchdog   90.00%  
2 m_axis_mm2s_ TOP_axis_master Bus Write to incorrect address Address Write register corruption Parity   99.50% 3.00%
Control plane state machine corruption Redundancy   99.80%  
Clocking corruption      
Driver/receiver failure      
Bus write with incorrect data Write data register corruption Parity   99.50%  
Control plane state machine corruption Redundancy   99.80%  
Clocking corruption      
Driver/receiver failure Loopback   90.00%  
Bus Read from incorrect address Read address register corruption Parity   99.50%  
Control plane state machine corruption Redundancy   99.80%  
Clocking corruption      
Receiver failure      
Bus read incorrect data Read Data register corruption Parity   99.50%  
Control plane state machine corruption Redundancy   99.80%  
Clocking corruption      
Receiver failure Parity   99.50%  
2 (cont'd)     Bus hang Control plane state machine corruption Redundancy   99.80%  
  External watchdog   90.00%  
3 mm2s_prmry_reset_out_n TOP_mm2s_reset_out Unintended reset Driver failure Supervision   90.00% 0.20% 0.10%
register corruption Parity   99.50%  
No reset out Driver failure Supervision   90.00%   0.10%
Register corruption Parity   99.50%  
4 CLK TOP_CLK No Clock Logic connection failure External watchdog   90.00%  
Incorrect clock frequency Clock divider failure External watchdog   90.00%  
5 axi_resetn TOP_axi_resetn Unintended reset Driver failure Supervision   99.50% 0.20%
Register corruption Parity   99.50%  
Reset signal timing too short Clock divider failure Supervision   90.00%  
  Register corruption Parity   99.50%  
Internal Signal block connections Signal/Bus Name ID TAG Fault Modes Fault Initiators Diagnostics Repeat EST DC Coverage  
1 b1_b2_signaling b1_b2_signal Incorrect data Data register corruption Data parity   99.50% 0.20% 0.10%
Incorrect clocking Clock divider failure External watchdog   90.00%  
Block Function Description ID TAG Fault Modes Fault initiators Diagnostics Repeat EST DC Coverage  
Function moves data between system memory and an AXI4-Stream device. The channel supports an AXI control stream for sending user application data to the target IP. For the S2MM channel, an AXI status stream is provided for receiving user application data from the target IP. MM2S_BLOCK Address or data storage corruption Single event upsets Storage parity   99.50% 6.00% 0.10%