The participants in a CAVP validation are the vendor and the CST lab. The CST lab independently tests cryptographic algorithms using the CAVS test tool. Either the vendor or the CST lab is allowed to perform the tests. CST labs are accredited under the NVLAP. The algorithms can be tested in a hardware environment or in simulation. A list of accredited labs can be found on the NIST IFT Computer Security Resource Center website [REF 17]. Also provided on this site are tests such as KATs [REF 18]. The AES and SHA cryptography used in Zynq UltraScale+ MPSoCs are approved cryptographic algorithms shown on the CAVP validation list [REF 19]. The following table lists the NIST validation numbers for the Zynq UltraScale+ MPSoC.
| CAVP Validation List | Validation Number |
|---|---|
| SHA3/384 | SHA-3 20 |
| Zynq UltraScale+ MPSoC AES-GCM Core | AES 4438 |
| Zynq UltraScale+ MPSoC XilSecure Library | A1940 |
The RSA algorithm used in the Zynq UltraScale+ MPSoC has the following two variances from the NIST standard:
- Uses a non-standard RSA modulus (4096 rather than 1024, 2048, or 3072).
- Omits the additional 01 appended to the message when using SHA3.
These slight variances are applied to boot and configuration cryptographic operations. Consequently, user implementations are not hampered by these limitations and nothing precludes the user`s ability to implement cryptographic algorithms that are fully compatible with the NIST standard. For more information on the variances of the RSA algorithm used in the Zynq UltraScale+ MPSoC, see the Variances Against NIST Cryptographic Standards for UltraScale, UltraScale+, and Zynq UltraScale+ Devices (XTP475), available on the AMD Design Security Lounge.