Solution Efficiencies for Dynamic Function eXchange Using Abstract Shells (WP533)

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1.0.1 English

Dynamic Function eXchange is a powerful capability within AMD FPGAs and adaptive SoCs that expands the flexibility of the silicon. Functions can be uploaded on the fly, delivering new functionality to one part of the device while the rest remains operational, expanding the effective usage of the device while reducing downtime. This time-multiplexed silicon usage approach allows you to do more with less, providing a critical advantage for designers looking to save cost, power, and time.

DFX also enables multi-user environments, allowing multiple groups or multiple companies to share the programmable logic space. One group (call them the primary user) creates the infrastructure of the design, from board-level considerations like memory access and communication links to safety and security details and runtime managers. The primary user locks down this static platform and leaves one or more empty work spaces for other groups (secondary users) to fill.

However, DFX requires some upfront considerations:

  • DFX designs require a specific design structure and layout to match the chip-within-a-chip paradigm. This more rigid structure can incur a penalty in the form of a longer design processing time.
  • Accelerated functions can be delivered to work spaces that are within platforms on-premises or in the cloud. The standard Vivado DFX flow requires that the complete locked static image be present to provide the context to place and route these accelerated functions. This requirement could expose proprietary design information owned by the primary user in multi-user scenarios.
Figure 1. Concepts of Dynamic Function eXchange

DFX enables new possibilities, but these two operating conditions might not be desirable for all systems or designs. An enhanced approach is needed to alleviate these concerns.