The abstract shell flow can even help designs not using dynamic reconfiguration. Large FPGA designs can experience long compile times through place and route due to the sheer volume of information to be considered during this process. For these designs, especially in larger multi-SLR Virtex UltraScale+ devices, DFX can be used to establish an in-context hierarchical design (HD) flow solution. This reduces the granularity of design iterations by segmenting the design into smaller, more manageable pieces. You set up the hierarchy to have a thin top-level wrapper and multiple RPs. When a minor iteration is required within one portion of the design, only that RM must be re-implemented. The abstract shell flow further enhances this approach by carving away the rest of the design, focusing attention on the modified module, significantly reducing compile time.
This in-context HD approach requires a segmented and floorplanned design. Resource utilization or performance limited designs are not good candidates for this methodology because applying DFX prevents logic optimization across boundaries and restricts placement within the target Pblocks. However, if your design can be divided into independent building blocks that occupy their own regions of the device, DFX with the abstract shell flow can greatly improve productivity when making small design changes.
In the following image, a four-SLR VU13P is divided into four reconfigurable partitions, one per SLR. Each RP can be extracted as an abstract shell, allowing each to be implemented independently. These abstract shells can be shared with different team members or simply run in parallel. When each region is complete, the RM-level checkpoint is linked with the routed-and-locked top-level checkpoint before bitstream generation is done.
