Validation Checklist - Validation Checklist - 6.3 English - XD056

Verify the following for each documented pipeline:

• sink caps match the intended preprocessing mode;

• preprocess-config is present only for internal PPE;

• PPE input buffers are compatible VVAS memory or importable DMA-BUF;

• no-PPE VART HW input is not system memory;

• external preprocessing produces the exact model tensor;

• CPU-written DMA-BUF input is synchronized before device read;

• repeated runs with identical input produce deterministic output.