Xilinx adopted the V4L2 framework for most of its video IP portfolio.
The currently supported video IPs and corresponding drivers are listed
under V4L2. Each V4L driver has a sub-page that lists driver-specific
details and provides pointers to additional documentation. The following
table provides a quick overview of the drivers used in this design.
Table : V4L2 Drivers Used in Capture Pipelines
Linux Driver |
Function |
|---|
Xilinx Video Pipeline (XVIPP) |
Configures video pipeline and register media, video and sub-device nodes. Configures all entities in the pipeline and validate links. Configures and controls DMA engines (Xilinx Video Framebuffer Write). Starts/stops video stream.
|
Xilinx Video Processing Subsystem
(Scaler Only configuration) |
Sets media bus format and resolution on input pad. Sets media bus format and resolution on output pad. (Output configuration can be different from the input configuration as
the block enables color space conversion and scaling).
|
MIPI CSI-2 Rx |
|
Xilinx Video Image Signal Processing
(ISP) |
|
Sony IMX274 Image Sensor |
Sets media bus format and resolution on output pad. Sets sensor control parameters: exposure, gain, test pattern, vertical flip.
|
OnSemi AR0231 Image Sensor |
Sets media bus format and resolution on output pad. Sets sensor control parameters: exposure, gain, test pattern, h/v flip, r/g/b balance.
|
MAX9286 GMSL Deserializer |
|
AXI-Stream Switch |
|
HDR Extract |
Sets media bus format and resolution on input pad. Sets media bus format and resolution on two output pads. Configure HDR Extract IP and stream data to produce Short Exposure Frame (SEF) and Long Exposre Frames(LEF).
|
HDR Merge |
Sets media bus format and resolution on two input pads. Sets media bus format and resolution on output pad. Configure HDR Merge IP and stream data to produce a single HDR Frame from SEF and LEF.
|
HDMI Rx Subsystem |
|