Clocks, Resets and Interrupts - 2020.2 English - XD336

The following table lists the clock frequencies of key ACAP components and memory. For more information refer to the Versal ACAP Technical Reference Manual (AM011).

Table 2 Table 1: Key Component Clock Frequencies

Component	Clock Frequency
ACPU	1,000 MHz
NOC	950 MHz
NPI	300 MHz
LPDDR	1,600
AIE	1,000

The following table identifies the main clocks of the PL design, their source, their clock frequency, and their function.

Table 3 Table 2: System Clocks

Clock	Clock Source	Clock Frequency	Function
pl0_ref_clk	CIPS	100 MHz	Clock source for clocking wizard.
clk_out1	Clocking wizard	150 MHz	AXI MM clock and AXI Stream clock used in the capture of platform2, display pipeline, and processing pipeline.
clk_out2	Clocking wizard	105 MHz	AXI-Lite clock to configure the different IPs in the design.
clk_out3	Clocking wizard	200 MHz	MIPI D-PHY core clock. Also the AXI MM clock and AXI Stream clock used in the capture pipeline of plaform2.
sys_clk0	SI570 (External)	200 MHz	Differential clock source used internally by the memory controller to generate various clocks to access DDR memory.
HDMI DRU clock	SI570 (External)	200 MHz	Clock for data recovery unit for low line rates.
HDMI GT TX reference clock	IDT 8T49N241(External)	Variable	GT Transmit clock source to support various HDMI resolutions.
HDMI GT RX reference clock	Si570 (External);	Variable	GT receive clock to support various HDMI resolutions.
Audio clock	Si570 (External)	Variable	Master reference clock to generate audio stream at the required sampling rate.

The PL0 clock is provided by the PLL inside the PMC domain and is used as the reference input clock for the clocking wizard instance. This clock does not drive any loads directly. A clocking wizard instance is used to de-skew the clock and to provide three phase-aligned output clocks, clk_out1, clk_out2 and clk_out3.

The clk_out2 is used to drive most of the AXI-Lite control interfaces of the IPs in the PL. AXI-Lite interfaces are typically used to configure registers and therefore can operate at a lower frequency than data path interfaces. Exception is the AXI-Lite interfaces of HLS based IP cores where the control and data plane use either clk_out1 or clk_out3.

The clk_out1 clock drives the AXI MM interfaces and AXI Stream interfaces of the display pipeline and processing pipeline. It also drives AXI MM interfaces and AXI Stream interfaces of the capture pipeline of platform2. The clk_out3 clock drives the AXI MM interfaces and AXI Stream interfaces of the capture pipeline in platform1.

For details on HDMI Tx and HDMI GT clocking structure and requirements refer to HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235) and HDMI GT Controller LogiCORE IP Product Guide (PG334). For HDMI Tx, an external clock chip is used to generate the GT reference clock depending on the display resolution. Various other HDMI related clocks are derived from the GT reference clock and generated internally by the HDMI GT controller; only for the DRU a fixed reference clock is provided externally by a Si570 clock chip.

For details on the various clock chips used refer to the VCK190 Evaluation Board User Guide (UG1366).

The master reset (pl_resetn0) is generated by the PS during boot and is used as input to the four processing system (PS) reset modules in the PL. Each module generates synchronous, active-Low and active-High interconnect and peripheral resets that drive all IP cores synchronous to the respective, clk_out0, clk_out1, and clk_out2 clock domains.

Apart from these system resets, there are asynchronous resets driven by PS GPIO pins. The respective device drivers control these resets which can be toggled at run-time to reset HLS- based cores. The following table summarizes the PL resets used in this design.

Table 4 Table 3: PL Resets

Reset Source	Purpose
pl0_resetn	PL reset for proc_sys_reset modules
rst_processor_150MHz	Synchronous resets for clk_out0 clock domain
rst_processor_105MHz	Synchronous resets for clk_out1 clock domain
rst_processor_200MHz	Synchronous resets for clk_out3 clock domain
lpd_gpio_o 0	Asynchronous reset for the video mixer IP
GPIO for Single Sensor platform
lpd_gpio_o 1	Asynchronous reset for the HDR extract IP
lpd_gpio_o 2	Asynchronous reset for the HDR merge IP
lpd_gpio_o 3	Asynchronous reset for the ISP IP
lpd_gpio_o 4	Asynchronous reset for the VPSS CSC IP
lpd_gpio_o 5	Asynchronous reset for the frame buffer write IP
lpd_gpio_o 6	Asynchronous reset for the sensor
GPIO for Quad Sensor platform
lpd_gpio_o 1	Asynchronous reset for the demosaic IP stream 0
lpd_gpio_o 2	Asynchronous reset for the VPSS CSC IP stream 0
lpd_gpio_o 3	Asynchronous reset for the frame buffer write IP stream 0
lpd_gpio_o 4	Asynchronous reset for the ISP IP stream 1
lpd_gpio_o 5	Asynchronous reset for the VPSS CSC IP stream 1
lpd_gpio_o 6	Asynchronous reset for the frame buffer write IP stream 1
lpd_gpio_o 7	Asynchronous reset for the ISP IP stream 2
lpd_gpio_o 8	Asynchronous reset for the VPSS CSC IP stream 3
lpd_gpio_o 9	Asynchronous reset for the frame buffer write IP stream
lpd_gpio_o 10	Asynchronous reset for the ISP IP stream 3
lpd_gpio_o 11	Asynchronous reset for the VPSS CSC IP stream 3
lpd_gpio_o 12	Asynchronous reset for the frame buffer write IP stream 3
GPIO for HDMI RX platform
lpd_gpio_0 1	Asynchronous reset for the VPSS CSC IP
lpd_gpio_0 2	Asynchronous reset for the frame buffer write IP

The following table lists the PL-to-PS interrupts used in this design.

Table 5 Table 4: Interrupts

Interrupt ID	Instance
pl_ps_irq0	HDMI GT Controller
pl_ps_irq1	HDMI Tx subsystem
pl_ps_irq2	Video Mixer
pl_ps_irq3	HDMI I2C
pl_ps_irq4	AXI Performance Monitor
Interrupts specific to Single Sensor platform
pl_ps_irq5	Audio formatter memory-mapped to stream
pl_ps_irq6	MIPI RX subsytem
pl_ps_irq7	MIPI I2C
pl_ps_irq8	Frame buffer write interrupt
Interrupts specific to Quad Sensor platform
pl_ps_irq5	Audio formatter memory-mapped to stream
pl_ps_irq6	MIPI RX subsytem
pl_ps_irq7	MIPI I2C
pl_ps_irq8	Frame buffer write stream 0
pl_ps_irq9	Frame buffer write stream 1
pl_ps_irq10	Frame buffer write stream 2
pl_ps_irq10	Frame buffer write stream 3
Interrupts specific to HDMI RX platform
pl_ps_irq5	Audio formatter memory-mapped to stream
pl_ps_irq6	Audio formatter stream to memory map
pl_ps_irq7	Frame buffer write interrupt
pl_ps_irq8	HDMI RX subsytem