Using the Netlist Insertion Flow - 2023.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2023-10-18
Version
2023.2 English

In this flow, you mark the nets in the block design for debug that you are interested in analyzing in the Vivado Hardware Manager. Marking nets for debug in the block design offers more control in terms of identifying debug signals during coding, and enabling/disabling debugging after the netlist has been generated.