Using the HDL Instantiation Flow in IP Integrator - 2024.1 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2024-05-30
Version
2024.1 English

For debugging the elements of a block design using the Vivado Hardware Manager, the IP integrator provides two distinct IP cores:

  • Integrated Logic Analyzer (ILA): This is a legacy debug core for block designs, that is no longer recommended for use. The Integrated Logic Analyzer (ILA) debug core lets you perform in-system debugging of implemented block designs to monitor signals in the design, to trigger on hardware events, and to capture data at system speeds. Detailed documentation on the ILA debug core can be found in the Integrated Logic Analyzer LogiCORE IP Product Guide (PG172).
  • System ILA: The System Integrated Logic Analyzer (System ILA) debug core is a logic analyzer that lets you monitor interfaces and signals in IP integrator block design, to trigger on interface and signal related hardware events, and to capture data at system speeds. The System ILA debug core offers AXI interface debug and monitoring capability along with AXI4-MM and AXI4-Stream protocol checking.

The System ILA core is synchronous to the nets being monitored or debugged, so all design clock constraints applied to that particular clock domain are also applied to the components of the System ILA core. Detailed documentation on the System ILA core IP can be found in the System Integrated Logic Analyzer LogiCORE IP Product Guide (PG261).

Note: Existing block designs can continue to use the ILA debug core. However, new block designs should use the new System ILA debug core to take advantage of the advanced features and ease-of-use of this core.