Supported Project Structures to Export to Vitis - 2023.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2023-10-18
Version
2023.2 English

The hardware definition (XSA) supports the following use cases:

  • A single BD instantiated in an HDL wrapper containing IP, hierarchical IP, or user created hierarchy.
  • A single BD instantiated in an HDL wrapper, where the wrapper contains additional non-hierarchical IP. The address map is fully contained on the BD.
  • A single MicroBlaze MCS instantiated in an HDL wrapper.

The following use cases will export, but are not fully supported:

  • Multiple BDs instanced in an RTL wrapper, where the connectivity between the BDs is contained in the RTL wrapper.
  • Multiple hierarchical IPs instanced in an RTL wrapper where the connectivity between the hierarchical IPs is contained in the RTL wrapper.
  • Mix of BDs and hierarchical IPs instanced in the RTL wrapper where the connectivity between the BDs and the hierarchical IPs is contained in the RTL wrapper.
  • Packaged BDs instantiated in an RTL wrapper.
  • Single BD instantiated in an HDL wrapper where the BD contains one or more packaged BD IP instances.