Prioritizing Interfaces for Automatic Inference - 2023.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2023-10-18
Version
2023.2 English

In some cases you need to specify the order in which interfaces are inferred rather than letting the tools automatically infer them. The Module Reference feature allows the user to prioritize the order of the interface inference. There are several attributes that can be used to infer interfaces.

For a particular interface, you might have slightly different physical pin (port) names than that prescribed in the standard. In such cases, specify the following attribute on the Tcl command line:

(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 axi_stream_s2c TREADY"
 *)output axi_stream_s2c_tready,

This attribute is inserted above the port definition in the HDL code, and specifies that the interface to be inferred has a VLNV of xilinx.com:interface:axis:1.0, its name is axi_stream_s2C, with a logical pin name TREADY to be mapped to the physical pin name axi_stream_s2c_tready. This attribute has the highest priority than other inferencing attributes.

If you have multiple versions of an interface that are slightly different in behavior or ports, use the X_INTERFACE_PRIORITY_LIST attribute to infer one over the other. The Verilog syntax for this is, as follows:

(* X_INTERFACE_PRIORITY_LIST = "xilinx.com:dsv:dsv_axis:3.0" *)
module axi_stream_gen_check #(
 ....
 ....
)

The VHDL syntax is, as follows:

entity HDMI_TX_INTF is
 Port (
-- put ports here
);

attribute X_INTERFACE_PRIORITY_LIST : string;
attribute X_INTERFACE_PRIORITY_LIST of HDMI_TX_INTF : entity is 
"xilinx.com:user:my_hdmi:3.0 xilinx.com:cust:cust_hdmi:4.0";
end HDMI_TX_INTF;

This attribute infers the specified interface as opposed to any other similar types of interfaces in the repository. This attribute needs to be inserted before the module definition in Verilog, and in the entity body in VHDL. This attribute has the second highest priority.

Interface inferencing can also be done by adding properties in the project as shown in the following code snippet:

set_property ip_interface_inference_priority xilinx.com:user:my_axis:2.0 
[current_project]

This has the third highest priority.

Finally, the repository ordering in the settings of the project determines the order of inferencing. As can be seen in the following figure, there are two repositories containing custom interfaces added to the project. The repository specified at the top:

C:/tutorials/2018.2/if_12/if_repo 

takes precedence over

C:/tutorials/2018.2/mod_ref/if_12/myipdir.

Typically, if you follow the naming conventions, then just adding the repositories in the project should be sufficient to infer an interface. See the following figure.

Figure 1. Add Repositories Containing Interfaces, Based on Priority