Non-Project Script - 2023.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2023-10-18
Version
2023.2 English

The following is a sample script for creating a block design in non-project mode.

#Set the target part, target language, and board part
set_part xc7k325tffg900-2
set_property target_language VHDL [current_project]
set_property board_part xilinx.com:kc705:part0:0.9 [current_project]
set_property default_lib work [current_project]

#Create block design using a tcl script
source create_bd.tcl

#Alternatively, you can read an existing block design 
read_bd ./bd/mb_ex_1/mb_ex_1.bd
open_bd_design ./bd/mb_ex_1/mb_ex_1.bd

#If the block design is the top-level hierarchy, then create and add wrapper file
make_wrapper -files [get_files  ./bd/mb_ex_1/mb_ex_1.bd] -top
read_vhdl  ./bd/mb_ex_1/hdl/mb_ex_1_wrapper.vhd

#Alternatively, you can read a top level RTL file
read_vhdl top.vhd

#Read constraints
read_xdc top.xdc

#If the block design does not have the output products generated, generate the output products needed for synthesis and implementation runs
set_property synth_checkpoint_mode None [get_files ./bd/mb_ex_1/mb_ex_1.bd]
generate_target all [get_files ./bd/mb_ex_1/mb_ex_1.bd]

#Run synthesis and implementation
synth_design -top mb_ex
opt_design
place_design
route_design
write_bitstream mb_ex.bit

#Export the implemented hardware system to the Vitis environment
write_hw_platform -fixed -force -file ./mb_ex.xsa