NoC IP DDR4 Memory Controllers - 2023.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2023-10-18
Version
2023.2 English

The DDR4 memory controllers (DDRMCs) are integrated into the axi_noc IP. The IP customization in the Vivado IP integrator also allows connecting memory controllers to the NoC and configuring the controllers and external DDR memory parameters. An instance of the axi_noc IP can be configured to include one, two, or four instances of the integrated DDRMCs. If two or four instances of the DDRMCs are selected, the DDRMCs are configured to form a single interleaved memory to all masters connected through the NoC.

In the IP integrator, the placement of your DDR memory controller might be different from your implementation. During the implementation phase, your package pin assignments are considered and the DDR memory controller might be moved. To ensure alignment, assign your DDR memory appropriately in the IP integrator.