Module Reference in a Non-Project Flow - 2023.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2023-10-18
Version
2023.2 English

The following is a sample script for opening a block design that uses the Module Reference feature, and contains referenced modules.

Important: The RTL source files for the referenced modules must be read prior to opening the block design.
# Specify part, language, board part (if using the board flow)
set_part xc7k325tffg900-2
set_property target_language VHDL [current_project]
set_property board_part xilinx.com:kc705:part0:0.9 [current_project]
set_property default_lib work [current_project]

# The following line is required for module reference and also for
# third-party synthesis flow
set_property source_mgmt_mode All [current_project]

# Read the RTL source files for referenced modules prior to reading 
# and opening the Block Design
read_verilog *.v
read_vhdl *.vhdl

# Read and Open the Block Design
read_bd ./bd/mb_ex_1/mb_ex_1.bd
open_bd_design ./bd/mb_ex_1/mb_ex_1.bd

# Add the HDL Wrapper for the Block Design
read_vhdl ./bd/mb_ex_1/hdl/mb_ex_1_wrapper.vhd

# Write hardware definition
write_hwdef -file mb_ex_1_wrapper.hwdef
set_property source_mgmt_mode All [current_project]
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1

# Implement
synth_design -top mb_ex_1_wrapper
opt_design
place_design
route_design
write_bitstream top

# For exporting the design to Vitis, add the following commands.
write_mem_info ./top.mmi
write_hw_platform -fixed -force  -file <path_to_xsa>/<xsa_name>.xsa