Limitations of the Module Reference Feature - Limitations of the Module Reference Feature - 2026.1 English - UG994

The following limitations exist in the Module Reference feature:

• Because a module reference is not an IP, you cannot specify the Vendor, Library, Name, and Version (VLNV).
• VHDL and Verilog are the only supported languages for module definition. A block design containing a module reference cannot be packaged as an IP. Instead, package the module as an IP separately, and then package the BD including that IP.
• Module Reference blocks cannot be opted out of upgrade while migrating a design from a previous version of Vivado.
• A ModuleRef must not contain CIPS or NOC IP.
• A ModuleRef cannot instantiate one or more DCP modules.
• A ModuleRef cannot instantiate one or more ModuleRefs (Nested ModuleRefs).
• A ModuleRef cannot instantiate a BD using block design container (BDC) technology.
• BD/ XCI are synthesized in out-of-context (OOC) inside module referenced RTL.
  Tip: SystemVerilog and VHDL 2008 are not supported for the module or entity definition at the top-level of the RTL module.
• When you have multiple instances of a module reference on a BD canvas, the instance names in the RTL hierarchy must be unique. You must make all the instance name unique to ensure that there are no conflicts. Alternatively, a BDC can be used. If the module reference is in the BDC, and the BDC is instantiated multiple times, the BDC takes care of making the instance names unique.
• Recursive components (modules that instantiate themselves directly or indirectly) are not supported for inclusion in a Block Design (BD). While recursive instantiation is a valid construct in RTL and is demonstrated in UG901, such modules are treated as incompatible when referenced in a BD.