Interface Type Settings - 2024.1 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2024-05-30
Version
2024.1 English

AXI Port

There must be at least one enabled AXI port master interface within the platform. Once enabled, AXI port interfaces have the following settings:

  • Memport: specifies the memory interface type.
  • SP Tag: a user-defined tag that can be used to reference the port in v++ in addition to the physical port name (optional). This tag must be unique.
  • Memory: specifies the associated MIG IP instance and address segment (optional). This option must reference an existing.
Note: Enabling an interface does not change the block design or the IP parametrization in any way. The block design captures this additional meta-data so that the AMD Vitis™ tool knows what interfaces, clocks, resets, and so forth, are available to be used by the hardware functions.

AXI Stream Port

These ports have the following settings:

  • Type: Specifies the type as M_AXIS for a general-purpose AXI master port or S_AXIS as a high-performance AXI slave port.
  • SP Tag: A user-defined tag that can be used to reference the port in v++ in addition to the physical port name (optional). This tag must be unique.

Clock

A platform can have one or more clocks. There must be at least one enabled clock interface within the platform. Once enabled, clock ports have the following settings:

  • ID: specifies the numeric id of the clock. This value must be unique and greater than 0.
  • Is Default: specifies the default clock for the platform. There must be one default clock identified.
  • Proc Sys Reset: identifies the associated reset block for the clock that provides the synchronized resets. Every clock must have a Processor System Reset IP block to synchronize the reset to these respective clock domains.
  • Status: defines whether the clock rate is fixed or scalable.
  • Frequency: specifies the clock frequency in MHz.
    Note: You must add PFM.CLOCK property to the external clock port. The property should be assigned to the input clock and clock wizard output clock port only.

Interrupt

There are no settings for interrupt interfaces. Interrupts are typically connected in platform via Concat block. The input of the Concat block can connect to multiple interrupt sources. It's possible for platforms to leave the input of the Concat block unconnected such that interrupts from hardware functions can connect to this unconnected input.

Memory

Specifies the memory subsystem if defined within the platform. There are no settings for this type.

Platform Name

Assigns the name, board, vendor, and version of the platform.